CANCELLED: FPGA Training with Intel

Thu, Mar 19, 2020, 10:00 am to 4:30 pm
120 Lewis Science Library
Faculty, graduate students, researchers and technical staff
Intel Corporation

This is workshop is open to all members of the PU community. Lunch will be provided to RSVPs.

10:00 AM-12:00 PM Introduction to Field-Programmable Gate Arrays (FPGAs)

12:00 PM-1:00 PM Lunch

The afternoon session will focus on specialized training. For those just looking for an overview of FPGAs, the morning session should be sufficient.

1:00 PM-2:00 PM Session 1
-- OneAPI for FPGA flow
-- Data Parallel C++ (DPC++) / SYCL

2:15 PM-3:15 PM Session2
-- OpenCL for FPGA flow

3:30-4:30 PM Session 3
-- High Level Synthesis (HLS) C++ for FPGA flow

Instructor Bio: Jeff Nigh has been involved with Programmable Logic for over 30 years starting in Avionics design for Rockwell Collins working on FPGAs for cockpit displays and for the last 19 years with Intel in the Intel Programmable Solutions Group (FPGA) in Field Applications Engineering, technical account management and most recently as a Technical Solutions Specialist for the FPGA acceleration products.

Research Computing recently installed four Intel FPGAs on the Della cluster. After attending this workshop you should have the skills needed to start using these devices. If you have an account on Della then use this command to connect: ssh The node is also available. Each node has 2 FPGAs. For all questions about the FPGAs on Della please write to

For questions about this workshop:

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